1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of testing the semiconductor memory device.
2. Description of the Related Art
To test a semiconductor memory device such as a dynamic semiconductor memory (DRAM) under manufacture, conventionally, data was sequentially written to/read from all address regions in rows and columns of a memory cell array, and an external tester received the read data to determine whether it shows Pass or Fail. This test was conducted at once for data corresponding to the number of data input/output lines or in units of data input/output bits. The number of data input/output lines is 4, 8, 16, . . . in a versatile DRAM of, e.g., 512 Mbits and it is 128, . . . in a DRAM of, e.g., 32 Mbits, which is embedded in a logic LSI.
With a considerable increase in capacity, however, an address region increases in storage space and accordingly test time is remarkably lengthened. This problem will be more serious.
The inventors of the present application have achieved a flash write technology in a multiport dynamic semiconductor memory (multiport DRAM) used in an image memory (“Toshiba CMOS Memory Data Book,” Toshiba Corporation, 1996, p.92). The flash write technology allows image data to be transferred at once to one row of the memory in write mode.